DDR5 memory standard: An introduction to the next generation of DRAM module technology

Dual 32-bit subchannels

DDR5 splits the memory module into two independent 32-bit addressable subchannels to increase efficiency and lower the latencies of data accesses for the memory controller. The data width of the DDR5 module is still 64-bit. However, breaking it down into two 32-bit addressable channels increases overall performance. For server-class memory (RDIMMs), 8-bits are added to each subchannel for ECC support for a total of 40-bits per subchannel, or 80-bits per rank. Dual rank modules feature four 32-bit subchannels.

Module key

The notch in the centre of the module acts like a key, aligning with DDR5 sockets to prevent DDR4, DDR3 or other unsupported module types from being installed. Unlike DDR4, DDR5 module keys differ between module types: UDIMM and RDIMM

On-die ECC

On-die ECC (Error Correction Code) is a new feature designed to correct bit errors within the DRAM chip. As DRAM chips increase in density through shrinking wafer lithography, the potential for data leakage increases. On-die ECC mitigates this risk by correcting errors within the chip, increasing reliability and reducing defect rates. This technology cannot correct errors outside of the chip or those that occur on the bus between the module and memory controller housed within the CPU. ECC-enabled processors for servers and workstations feature the coding that can correct single or multi-bit errors on the fly. Extra DRAM bits must be available to allow this correction to occur, as featured on ECC-class module types such as ECC unbuffered, registered and load reduced.

Additional temperature sensors

Server-class DDR5 RDIMMs add temperature sensors to the ends of the modules to monitor thermal conditions across the length of the DIMM. This allows for more precise control of system cooling, as opposed to the throttling of performance seen in DDR4 for high temperatures.